Model-to-Silicon
for Physical AI
Workload-specific silicon with software-style amortization
Investor Presentation · 2026
The Belief
The future of Physical AI belongs to workload-specific silicon
- AI is moving from the datacenter to the edge. Physical AI is embodied - it runs on robots, drones, vehicles, factory floors. Today, this market is large but neglected
- Every Physical AI deployment is device-specific and workload-specific - locked to a model, a pipeline, a power envelope, a form factor. The software stack is already specialized top to bottom
- But that specialization stops at the chip. The silicon underneath is still general-purpose. The chip is the last layer that hasn't caught up
- The chip is no longer the unit of value. The deployed workload is
The Problem
The old approach doesn't work for Physical AI
- The semiconductor industry's 2–3 year design cycles and billion-dollar budgets were built for general-purpose. Legacy vendors can't deliver specialized silicon at the pace or price the market demands
- Power, thermals, latency, wake-up time, battery life, and BOM should be architecture constraints, not afterthoughts
- Data-center chips optimize for dense, synchronous, high-batch workloads. Physical AI is sparse, asynchronous, and bursty
These problems appear so fatal to the viability of specialized edge silicon, customers are left wondering:
how do Tesla, Rivian, and XPeng solve it?
Market Leaders Approach
How do Tesla, Rivian, and XPeng solve it?
- Just like the hyperscalers before them, the leaders in Physical AI long ago came to the conclusion that the existing silicon vendors didn't understand them - and never would
- They developed their own custom silicon with tightly integrated hardware, firmware, and software - designed from the workload up
- But these chips aren't available to the rest of the market
- Everyone else is left to navigate an unforgiving sea of general-purpose components - without the scale, resources, or expertise of a Tesla or a Rivian
Why Now
Three forces are converging
- Physical AI workloads are overwhelmingly AI inference. Inference is a fixed compute graph with known data flow, precision, and latency requirements. The model becomes the design specification for silicon
- Model builders (from Ultralytics to Physical Intelligence) are becoming synonyms for a function, not an architecture. Models absorb every required block into predictable releases, like software. Models ship on a schedule now - the hardware has to follow
- AI agents and foundational models recently made a huge leap forward - what was previously possible only in SW space now entered HW, what took teams of dozens of engineers years can be explored in hours
The Insight
AI agents don't need to respect human boundaries in system design
If you can vibe-code directly in assembly, you don't need a compiler. If you can reliably vibe-code RTL, you don't need the layers above it
Models are fixed (not turing-complete) compute graphs which allows agents to reason about model structure, quantization, data movement, memory layout, compute topology, scheduling, microarchitecture, and RTL as coupled choices
This collapses hardware/software co-design into an end-to-end optimization problem: given a workload and constraints, find the best implementation across the software-hardware boundary
What is required for it to work?
You can't ask AI to create chip design from scratch — that's an infinite search problem. Agents need a real, open, silicon-proven substrate they can reason about, compose, and specialize
The Solution
Agentic search for the best MoM (Model-on-Module) design
Compute & local memory
Basic composable unit
Scale to workload
Ready for deployment
We are building the platform that will make specialized chips as easy to ship as software
Platform
CORE-ET: open, composable, silicon-proven IP building blocks
🤖 Minion Core
Tightly optimized, dual-threaded RISC-V core. Low-power. Small enough to replicate aggressively, predictable enough to compose into larger fabrics. Vector and tensor operations on up to 256-bit FP or 512-bit integer data per clock cycle
🏘️ Compute Tile (8 cores)
Atomic unit of design. First level of cache hierarchy. ~1 TOPS at 0.5W. Coordinated, efficient, shaped for systolic-array-like architectures
🌐 Composable Fabric
Scale from edge (8-core) to embedded (256-core) to datacenter-class (4096 core). NEMI NoC: mesh with Static XY routing. AXI/APB support. Native broadcast
🧠 iRAM Memory Advantage
| iRAM | SRAM | LPDDR5 | HBM3 | |
|---|---|---|---|---|
| Bandwidth | 0.25–1 TB/s | ~1 TB/s (mid-compute) | 0.25 TB/s | 1 TB/s |
| Latency | 6–9 ns | 3–4 ns | 70–100 ns | 100–150 ns |
| Power | 0.2–0.6W active/ 1mW standby | 12–60W | 1–2W | 5–9W |
💻 Software Building Blocks
Traction
Real silicon, real software, real momentum
Esperanto Technologies develops manycore RISC-V chip. 10 years and over $200M invested in production-grade IP. Taped out 1088-core ET-SoC-1 - 150 TOPS at under 50W
AiNEKKO acquires Esperanto IP. Announces open-source strategy
Merger with Veevx - adds MRAM/iRAM memory technology and experienced physical design team
Erbium tile tapeout on TSMC shuttle. First ever fully open tape out. Agentic system porting any model from Hugging Face to it
Model-to-silicon with 100x+ optimizations
🏭 Community & Makers
Raspberry Pi, Crowd Supply - bootstrapping the hardware community and maker ecosystem
🧠 Model Builders
Hugging Face, Ultralytics, Liquid AI - co-optimizing models for edge silicon
🔗 Open Source Ecosystem
Part of Eclipse Foundation, OpenHW Group and AI Foundry. Organizing AI Devroom at FOSDEM with 3000+ participants 2 years in a row and AI Plumbers conference
Market Opportunity
The edge AI chip market is exploding
Embedded AI Tiers by Processing Performance (Source: Gartner)
The Future of Embedded AI (Source: Gartner)
AiNEKKO's Position
We already service function-specific and application-specific use cases today. Our roadmap is purposefully aligned with the multimission and embodied AI tiers, enabling customers to stay on the cutting edge
* Source: Edge-AI Market Analysis, SHD Group, April 2025
Business Model
New economics of composable silicon
Platform + Silicon Sales
Sell composable compute tiles and reference designs. Customers get custom-grade chips without custom tape-out costs. Tape-out every 9 months vs. every 2–3 years
AI-Designed Silicon as a Service
Agents compose and specialize chips from our substrate for specific workloads. Chiplet recomposition - building blocks taped out once, reused many times
The Structural Advantage
- Iteration becomes cheap - composable substrate eliminates full re-spins
- Exploration becomes parallelizable - agents search design space autonomously
- Specialization at small scale - viable economics for niche markets
- Open ecosystem - community contributes, no license friction
Competitive Landscape
A fundamentally different approach
| NVIDIA Jetson | Custom ASIC (Broadcom/Marvell) |
Taalas | AiNEKKO | |
|---|---|---|---|---|
| Focus | GPU | Single customer ASIC | Model→Verilog | Composable edge silicon |
| Open Source | ❌ | ❌ | ❌ | ✅ |
| Silicon-proven | ✅ | ✅ | ✅ | ✅ |
| Agent-native | ❌ | ❌ | Partial | ✅ |
| Edge optimized | Partial | Varies | ❌ | ✅ |
| Mutable weights | ✅ | ✅ | ❌ | ✅ |
| Time to chip | N/A (off-shelf) | 2–3 years | Up to a year | 1-9 months |
AiNEKKO is the only player with silicon-proven, open-source, agent-native, edge-optimized composable silicon. We're not building one chip - we're building the platform for the next thousand
The Challenges
We see the risks clearly
- Technical challenges? These days any experienced engineer can try vibecoding a chip. The tools are available. The real challenge is applying good technical taste, physical design skills and having relationships with fabs — we've got all that converged on our team
- Market challenges? Physical AI models are emerging rapidly. AI-first companies optimizing their workloads end-to-end are winning over incumbents. The market is early but rapidly growing. We see this as a "choppy sea" race and we're preparing for that from the get-go
- Team challenges? We are rethinking how the team should be structured in the age of agentic systems, redefining the lines between SW‑HW, digital‑analog and tightening iteration cycles. Nobody has the right answers yet, but we have the luxury of fast experiments with no legal and IP constraints
- Capital challenges? Hardware is still capital-intensive, but not as expensive as smallest-node tapeouts required for data centers. Economics and timelines work for us — 12/16 nm processes are well suited for the edge
The Team
Built to win this race with experience and execution
Our team has been in the trenches of both traditional, and AI-focused computing and how end-to-end computing systems are built, bought, sold, and operated.
- Tanya Dadasheva, Co-founder & CEO: Deep semiconductor and OSS investing background at Almaz Capital. Operator who understands both the technology and the market. Brings unique go-to-market understanding for both traditional and AI-focused silicon
- Roman Shaposhnik, Co-founder & CTO: Former CTO & co-founder at ZEDEDA; previously Pivotal, Cloudera, ASF. Open-source veteran and systems architect. Brings the community playbook that makes open silicon viable. Long track record building talented teams developing industry-leading technology
- Doug Smith, Co-founder & CSO: Former CEO at Veevx; 20+ years at Broadcom building production memory technology. Brings MRAM/iRAM expertise and a seasoned physical design team with dozens of successful tapeouts
- Gianluca Guida, Founding Engineer & VP of Agentic Engineering: Former Sr. Engineer at RIVOS; previously Apple, XenSource, VMWare. Deep systems and low-level, end-to-end engineering. Deep technologist and a leader of the infrastructure tribe
Team
Previously building Esperanto, Tenstorrent, AMD GPUs, central engineering Broadcom, silicon market M&As, edge market sales/bizdev
Advisors
Backed By
WI Harper
Silicon Catalyst
Alexander Galitsky
Constructor Capital
The Opportunity
The next race is to make
the next thousand chips
We are raising $20M to enable it
© 2026 Ainekko, Co.